我想ISE设计一个数字钟,但是出现了Xst:871 - "topclock.v" line 33: Invalid use of input signal as target.ERROR:Xst:871 - "topclock.v" line 40: Invalid use of input signal as target.这两个错误,求大神解答一下这是什么原因
module topclock(
input CP,
input nCR,
input EN,
input Adj_Hour,
input Adj_Min,
output [7:0] Hour,
output [7:0] Minute,
output [7:0] Second
);
supply1 Vdd;
wire SecH_EN,MinL_EN,MinH_EN,Hour_EN;
counter10 U1(Second[3:0],CP,nCR,EN);
counter6 U2(Second[7:4],CP,nCR,SecH_EN);
assign MinL_EN=Adj_Min? Vdd:(Second==8'h59);
assign MinH_EN=(Adj_Min&&(Minute[3:0]==4'h9))||(Minute[3:0]==4'h9)&&(Second==8'h59);
counter10 U3(Minute[3:0],CP,nCR,MinL_EN);
counter6 U4(Minute[7:4],CP,MinH_EN);
assign Hour_EN=Adj_Hour? Vdd:((Minute==8'h59)&&(Second==8'h59));
counter24 U5(Hour[7:4],Hour[3:0],CP,nCR,Hour_EN);
endmodule
module counter10(
input CP,
input nCR,
input EN,
output reg[3:0] Q
);
always@(posedge CP,negedge nCR)
begin
if(~nCR) Q<=4'b0000;
else if(~EN) Q<=Q;
else if(Q==4'b1001) Q<=4'b0000;
else Q<=Q+1'b1;
end
endmodule
module counter6(
input CP,
input nCR,
input EN,
output reg[3:0] Q
);
always@(posedge CP,negedge nCR)
begin
if(~nCR) Q<=4'b0000;
else if(~EN) Q<=Q;
else if(Q==4'b0101) Q<=4'b0000;
else Q<=Q+1'b1;
end
endmodule
module counter24(
input CP,
input nCR,
input EN,
output reg[3:0] CntH,
output reg[3:0] CntL
);
always@(posedge CP,negedge nCR)
begin
if(~nCR) {CntH,CntL}<=8'h00;
else if(~EN) {CntH,CntL}<={CntH,CntL};
else if(((CntH>2)||(CntL>9))||((CntH==2)&&(CntL>=3))) {CntH,CntL}<=8'h00;
else if((CntH==2)&&(CntL<3)) begin CntH<=CntH;CntL<=CntL+1'b1;end
else if(CntL==9) begin CntH<=CntH+1'b1;CntL<=4'b0000;end
else begin CntH<=CntH;CntL<=CntL+1'b1;end
end
endmodule
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